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| eeprom as8er128k32 austin semiconductor, inc. as8er128k32 rev. 3.0 1/02 austin semiconductor, inc. reserves the right to change products or specifications without notice. 1 general description the austin semiconductor, inc. as8er128k32 is a 4 megabit radiation tolerant eeprom module organized as 128k x 32 bit. user configurable to 256k x16 or 512kx 8. the module achieves high speed access, low power consumption and high reliability by employ- ing advanced cmos memory technology. the military grade product is manufactured in compliance to mil-std 883, making the as8er128k32 ideally suited for military or space applications. the module is offered as a 68 lead 0.990 inch square ceramic quad flat pack. it has a max. height of 0.200 inch. this package design is targeted for those applications which require low profile smt pack- aging. * contact factory for test reports. asi does not guarantee or warrant these performance levels, but references these third party reports. features ? access time of 150ns ? operation with single 5v + 10% supply ? power dissipation: active: 1.43 w (max), max speed operation standby: 7.7 mw (max), battery back-up mode ? on-chip latches: address, data, ce\, oe\, we\ ? automatic byte write: 10 ms (max) ? automatic page write (128 bytes): 10 ms (max) ? data protection circuit on power on/off ? low power cmos ?10 4 erase/write cycles (in page mode) ? software data protection ? ttl compatible inputs and outputs ? data retention: 10 years ? ready/busy\ and data polling signals ? write protection by res\ pin ? radiation tolerant: proven total dose 40k to 100k rads* ? operating temperature ranges: military: -55 o c to +125 o c industrial: -40 o c to +85 o c options markings ? timing 150 ns -15 ? package ceramic quad flat pack q no. 703 available as military specifications ? mil-std-883 pin assignment (top view) 68 lead cqfp 128k x 32 eeprom radiation tolerant eeprom memory array for more products and information please visit our web site at www.austinsemiconductor.com i/o0 i/o1 i/o2 i/o3 i/o4 i/o5 i/o6 i/o7 gnd i/o8 i/o9 i/o10 i/o11 i/o12 i/o13 i/o14 i/o15 9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61 res\ a0 a1 a2 a3 a4 a5 cs3\ gnd cs4\ we1\ a6 a7 a8 a9 a10 vcc 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 vcc a11 a12 a13 *a15 *a14 a16 cs1\ oe\ cs2\ nc we2\ we3\ we4\ nc nc rdy 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 i/o16 i/o17 i/o18 i/o19 i/o20 i/o21 i/o22 i/o23 gnd i/o24 i/o25 i/o26 i/o27 i/o28 i/o29 i/o30 i/o31 pin name function a0 to a16 address input i/o0 to i/o31 data input/output oe\ output enable ce\ chip enable we\ write enable v cc power supply v ss ground rdy/busy\ ready busy res\ reset functional block diagram *pin #'s 31 and 32, a15 and a14 respectively, are reversed from the as8e128k32. correct use of these address lines is required for operation of the sdp mode to work properly.
eeprom as8er128k32 austin semiconductor, inc. as8er128k32 rev. 3.0 1/02 austin semiconductor, inc. reserves the right to change products or specifications without notice. 2 notes: 1. rdy/busy\ output has only active low v ol and high impedance state. it can not go to high (v oh ) state. 2. v cc -0.5 < v h < v cc +1.0 3. x : don't care truth table mode ce\ oe\ we\ res\ rdy/busy\ 1 i/o read v il v il v ih v h 2 high-z dout standby v ih x 3 x x high-z high-z write v il v ih v il v h high-z to v ol din deselect v il v ih v ih v h high-z high-z xx v ih x --- --- x v il x x --- --- data\ polling v il v il v ih v h v ol dout (i/o7) program reset x x x v il high-z high-z wirte inhibit eeprom as8er128k32 austin semiconductor, inc. as8er128k32 rev. 3.0 1/02 austin semiconductor, inc. reserves the right to change products or specifications without notice. 3 *stresses greater than those listed under "absolute maximum ratings" may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. **junction temperature depends upon package type, cycle time, loading, ambient temperature and airflow, and humidity (plastics). absolute maximum ratings* voltage on vcc supply relative to vss vcc ....................................................................-0.6v to +7.0v operating temperature range (1) ..................-55 c to +125 c storage temperature range .........................-65 c to +150 c voltage on any pin relative to vss..............-0.5v to +7.0v (2) max junction temperature**.......................................+150 c thermal resistance junction to case ( q jc ): package type q...........................................11.3 c/w package type p & pn..................................2.8 c/w notes: 1) including electrical characteristics and data retention. 2) v in min = -3.0v for pulse width < 20ns. electrical characteristics and recommended dc operating conditions (-55 o c eeprom as8er128k32 austin semiconductor, inc. as8er128k32 rev. 3.0 1/02 austin semiconductor, inc. reserves the right to change products or specifications without notice. 5 electrical characteristics and recommended ac write characteristics (-55 o c < t a < +125 o c; vcc = 5v +10%) symbol parameter min (2) max units t as address setup time 0 ms t ah address hold time 150 ns t cs ce\ to write setup time (we\ controlled) 0 ns t ch ce\ hold time (we\ controlled) 0 ns t ws we\ to write setup time (ce\ controlled) 0 ns t wh we\ to hold time (ce\ controlled) 0 ns t oes oe\ to write setup time 0 ns t oeh oe\ to hold time 0 ns t ds data setup time 100 ns t dh data hold time 10 ns t wp we\ pulse width (we\ controlled) 250 ns t cw ce\ pulse width (ce\ controlled) 250 ns t dl data latch time 300 ns t blc byte load cycle 0.55 30 s t bl byte load window 100 s t wc write cycle time 10 (3) ms t db time to device busy 120 ns t dw write start time 150 (4) ns t rp reset protect time 100 s t res reset high time (5) 1s read timing waveform t acc t ce t oe t oh t df t dfr t rr high-z address ce\ oe\ we\ data out res\ data out valid v ih eeprom as8er128k32 austin semiconductor, inc. as8er128k32 rev. 3.0 1/02 austin semiconductor, inc. reserves the right to change products or specifications without notice. 6 byte write timing waveform (we\ controlled) byte write timing waveform (ce\ controlled) t res t rp high-z t oes t as t cs t ah t wc t ch t bl t oeh t wp t ds t dh t db t dw high-z v cc res\ rdy/busy\ d in oe\ we\ ce\ address v ol t res t rp high-z t oes t as t ws t ah t wc t wh t bl t oeh t cw t ds t dh t db t dw high-z v cc res\ rdy/busy\ d in oe\ we\ ce\ address v ol eeprom as8er128k32 austin semiconductor, inc. as8er128k32 rev. 3.0 1/02 austin semiconductor, inc. reserves the right to change products or specifications without notice. 7 page write timing waveform (we\ controlled) page write timing waveform (ce\ controlled) high-z high-z v cc res\ rdy/busy\ d in oe\ ce\ we\ address (6) a0 to a16 t res t rp t db t ds t dh t oes t cs t ch t blc t dl t wp t as t ah t bl t wc t oeh t dw high-z high-z v cc res\ rdy/busy\ d in oe\ we\ ce\ address (6) a0 to a16 t res t rp t db t ds t dh t oes t ws t wh t blc t dl t cw t as t ah t bl t wc t oeh t dw eeprom as8er128k32 austin semiconductor, inc. as8er128k32 rev. 3.0 1/02 austin semiconductor, inc. reserves the right to change products or specifications without notice. 8 data polling timing waveform an an din x dout x dout x t oe (7) t wc t oeh t ce (7) t oes t dw address ce\ we\ oe\ i\o7 notes: 1. t df and t dfr are defined as the time at which the outputs achieve the open circuit conditions and are no longer driven. 2. use this device in longer cycle than this value. 3. t wc must be longer than this value unless polling techniques or rdy/busy\ are used. this device automatically com- pletes the internal write operation within this value. 4. next read or write operation can be initiated after t dw if polling techniques or rdy/busy\ are used. 5. this parameter is sampled and not 100% tested. 6. a7 to a16 are page addresses and must be same within the page write operation. 7. see ac read characteristics. eeprom as8er128k32 austin semiconductor, inc. as8er128k32 rev. 3.0 1/02 austin semiconductor, inc. reserves the right to change products or specifications without notice. 9 toggle bit this device provides another function to determine the internal programming cycle. if the eeprom is set to read mode during the internal programming cycle, i/o6 will charge from "1" to "0" (toggling) for each read. when the internal pro- gramming cycle is finished, toggling of i/o6 will stop and the device can be accessible for next read or program. toggle bit waveform notes: 1) i/o6 beginning state is "1". 2) i/o6 ending state will vary. 3) see ac read characteristics. 4) any locations can be used, but the address must be fixed. dout 2 dout 2 dout dout 1 din t ce 3 t oe 3 t oeh t wc t dw 4 next mode t oes address ce\ we\ oe\ i/o6 software data protection timing waveform (in protection mode) t wc t blc { address data (each byte) 5555 aa aaaa or 2aaa 55 5555 a0 write address* write data v cc ce\ we\ t blc t blc * during this write cycle, data is physically written to the address provided. eeprom as8er128k32 austin semiconductor, inc. as8er128k32 rev. 3.0 1/02 austin semiconductor, inc. reserves the right to change products or specifications without notice. 10 software data protection timing waveform (in non-protection mode) functional description automatic page write page-mode write feature allows 1 to 128 bytes of data to be written into the eeprom in a single write cycle. following the initial byte cycle, an additional 1 to 128 bytes can be writ- ten in the same manner. each additional byte load cycle must be started within 30s from the preceding falling edge of we\ or ce\. when ce\ or we\ is kept high for 100s after data input, the eeprom enters write mode automatically and the input data are written into the eeprom. data\ polling data\ polling allows the status of the eeprom to be deter- mined. if eeprom is set to read mode during the write cycle, an inversion of the last byte of data to be loaded outputs from i/o's 7, 15, 23, and 31 to indicate that the eeprom is per- forming a write operation. rdy/busy\ signal rdy/busy\ signal also allows status of the eeprom to be determined. the rdy/busy\ signal has high impedance ex- cept in write cycle and is lowered to v ol after the first write signal. at the end of write cycle, the rdy/busy\ signal changes state to high impedance. res\ signal when res\ is low, the eeprom cannot be read or pro- grammed. therefore, data can be protected by keeping res\ low when v cc is switched. res\ should be high during read and programming because it doesn't provide a latch function. see timing diagram below. program inhibit program inhibit read inhibit read inhibit v cc res\ res\ signal diagram t wc address data (each byte) 5555 aa aaaa or 2aaa 55 5555 80 aaaa or 2aaa 55 v cc ce\ we\ 5555 aa 5555 20 normal active mode eeprom as8er128k32 austin semiconductor, inc. as8er128k32 rev. 3.0 1/02 austin semiconductor, inc. reserves the right to change products or specifications without notice. 11 we\, ce\ pin operation during a write cycle, address are latched by the falling edge of we\ or ce\, and data is latched by the rising edge of we\ or ce\. write/erase endurance and data retention time the endurance is 10 4 cycles in case of the page programming and 10 3 cycles in case of the byte programming (1% cumula- tive failure rate). the data retention time is more than 10 years when a device is page-programmed less than 10 4 cycles. rdy/busy\ signal rdy/busy\ signal also allows status of the eeprom to be determined. the rdy/busy\ signal has high impedance except in write cycle and is lowered to v ol after the first write signal. at the end of the write cycle, the rdy/busy\ signal changes state to high impedance. this allows many 58c1001 devices rdy/busy\ signal lines to be wired-or together. programming/erase the 58c1001 does not employ a bulk-erase function. the memory cells can be programmed 0 or 1. a write cycle performs the function of erase & write on every cycle with the erase being transparent to the user. the internal erase data state is considered to be 1. to program the memory array with background of all 0s or all 1s, the user would program this data using the page mode write operation to program all 1024 128-byte pages. data protection 1. data protection against noise on control pins (ce\, oe\, we\) during operation during readout or standby, noise on the control pins may act as a trigger and turn the eeprom to programming mode by mistake. to prevent this phenomenon, this device has a noise cancellation function that cuts noise if its width is 20ns or less in program mode. be careful not to allow noise of a width more than 20ns on the control pins. see diagram 1 below. 2. data protection at v cc on/off when v cc is turned on or off, noise on the control pins generated by external circuits (cpu, etc.) may act as a trigger and turn the eeprom to program mode by mistake. to prevent this unintentional programming, the eeprom must be kept in an unprogrammable state while the cpr is in an unstable state. note: the eeprom should be kept in unprogrammable state during v cc on/off by using cpu re- set signal. see the timing diagram below. diagram 1 data protection at v cc on/off *unprogrammable v cc cpu reset *unprogrammable eeprom as8er128k32 austin semiconductor, inc. as8er128k32 rev. 3.0 1/02 austin semiconductor, inc. reserves the right to change products or specifications without notice. 12 data protection cont. a. protection by res\ the unprogrammable state can be realized by the cpu's reset signal inputs directly to the eeprom's res pin. res should be kept v ss level during v cc on/off. the eeprom brakes off programming operation when res becomes low, programming operation doesn't fin- ish correctly in case that res falls low during programming operation. res should be kept high for 10ms after the last data inputs. see the timing diagram below. 3. software data protection to prevent unintentional programming, this device has the software data protection (sdp) mode. the sdp is enabled by inputting the 3 bytes code and write data in chart 1. sdp is not enabled if only the 3 bytes code is input. to program data in the sdp enable mode, 3 bytes code must be input before write data. this 4th cycle during write is required to initiate the sdp and physically writes the address and data. while in sdp the entire array is protected in which writes can only occur if the exact sdp sequence is re-executed or the unprotect sequence is executed. the sdp is disabled by inputting the 6 bytes code in chart 2. note that, if data is input in the sdp disable cycle, data can not be written. the software data protection is not enabled at the shipment. note: these are some differences between asi's and other company's for enable/disable sequence of software data protection. if these are any questions, please contact asi. protection by res\ program inhibit v cc res\ program inhibit we\ or ce\ 1 min 100 min 10 ms min chart 1 address 5555 aaaa or 2aaa 5555 write address data (each byte) aa 55 a0 write data} normal data input chart 2 address 5555 aaaa or 2aaa 5555 5555 aaaa or 2aaa 5555 data (each byte) aa 55 80 aa 55 20 eeprom as8er128k32 austin semiconductor, inc. as8er128k32 rev. 3.0 1/02 austin semiconductor, inc. reserves the right to change products or specifications without notice. 13 asi case #703 (package designator q) mechanical definitions* *all measurements are in inches. 4 x d2 4 x d1 4 x d b e pin 1 min max a 0.123 0.200 a1 0.118 0.186 a2 0.000 0.020 b 0.013 0.017 b d d1 0.870 0.890 d2 0.980 1.000 d3 0.936 0.956 e r 0.005 l1 0.035 0.045 symbol 0.010 ref 0.050 bsc asi package specifications 0.800 bsc detail a l1 0 o - 7 o r b a2 see detail a a d3 a1 eeprom as8er128k32 austin semiconductor, inc. as8er128k32 rev. 3.0 1/02 austin semiconductor, inc. reserves the right to change products or specifications without notice. 14 *available processes it = industrial temperature range -40 o c to +85 o c xt = extended temperature range -55 o c to +125 o c ordering information device number package type speed ns process as8er128k32 q -15 /* example: as8er128k32q-15/xt |
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